To implement the motion compensation inter-frame prediction, a method is utilized in which information indicating from which position in the preceding image a part of the present image has moved (i.e., a motion vector) is employed to reduce temporal redundancy. A block matching method is one of the methods for extracting the motion vector.
FIG. 10 is a diagram showing the principle of the block matching method.
As shown in FIG. 10, a coding frame image (target to be coded) and a search range frame image for detecting a motion vector are compared with each other to extract, from a search range 904 in a search range frame 903, a block (best matching block) 902 having the closest evaluation value (i.e. having the highest correlation) with respect to a target block to be coded (hereinafter, referred to as a coding target block) 906 in a frame to be coded (hereinafter, referred to as a coding frame) 905, thereby to detect a motion vector 901.
A motion vector detection circuit is an important circuit block that decides whether the coding efficiency is improved, i.e., whether a higher image quality is obtained from a smaller amount of codes. Thus, it is preferable that this circuit can widen the search range 904 and detect the motion vector 901 indicating a block that is closer to the coding target block 906, thereby to obtain a higher image quality. However, when the search range 904 is widened, problems occur that the scale of the motion vector detection circuit or the processing time is increased, and further the bus width is increased to supply a larger search range to the motion vector detection circuit.
Some conventional image coding apparatuses internally contain all coding circuits including a motion search unit for performing motion vector detection, to reduce the number of components.
For example, Japanese Published Patent Application No. Hei.10-108199 shows, in FIG. 1, an apparatus that implements inter-frame image predictive coding and, more particularly, an apparatus that outputs one kind of coded data from one image input. According to this apparatus, an image signal is inputted to an image input unit, and a motion search unit performs motion search, whereby a motion vector is finally obtained. A pixel value calculation unit subjects prediction error data to processing of DCT, quantization, inverse quantization, and inverse DCT processes. A variable length coding unit executes a variable length coding process, and a code output unit outputs a final code string. A frame memory, a frame memory control unit, control processors and a host interface are needed at that time, while when the host interface controls the image input unit, the motion search unit, the pixel value calculation unit and the variable length coding unit in time division, the control processors for the entire processing sections, such as the image input unit, the motion search unit, the pixel value calculation unit and the like can be consolidated.
More specifically, as shown in FIG. 5 of Japanese Published Patent Application No. Hei.10-108199, the frame control unit internally includes a frame memory index register, and then the control processor sets information in the frame memory index register for memory area dedication, thereby enabling to change a writing area in the frame memory for the image data that is inputted from the image input unit, or a writing area in the frame memory for a prediction image that is obtained by the pixel value calculation unit. It is specified in this application that this construction provides an image coding apparatus including fewer components, in which, for example, one external memory is provided.
The bandwidth that is required for transferring data corresponding to a coding target in a common image according to NTSC (720 pixels×480 lines×30 frames/sec) is given by Formula (1). The bandwidth that is required for transferring data corresponding to a search range in a case where the search range consists of 48 pixels×48 lines (±16 pixels in the horizontal direction, and ±16 lines in the vertical direction) is given by Formula (2).((720 pixels×480 lines+360 pixels×240 lines×2)×30 frames/sec×8 bit/pixel)×2=0.25 Gps   Formula (1)((720 pixels×480 lines+360 pixels×240 lines×2)×30 frames/sec×8 bit/pixel)+((720 pixels×480 lines)×(48 pixels×48 lines)/(16 pixels×16 lines)×30 frames/sec×8 bit/pixel)×2+((360 pixels×240 lines×2)×30 frames/sec×8 bit/pixel)×2=1.7 Gps   Formula (2)
The multiplier “2” at the end of Formula (1) represents writing and reading into/from the external memory.
The first term of Formula (2) represents writing of an prediction image (0.12 Gps), the second term represents reading of the search range (prediction image ) (only luminance components) (1.5 Gps), and the third term represents reading of color-difference components of the prediction image (0.08 Gps). The multipliers “2” in the second and third terms of Formula (2) result from bidirectional inter-frame prediction.
In the prior art, all of these processing are implemented by the transfer of data with an external memory that is connected via one data bus.
For example, as described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997, when 32 bit-width data is transferred in an 81 MHx operation, the data transfer is performed at a bandwidth of 2.6 Gps, and thus there is a margin that is approximately 1.5 times larger than the necessary data transfer amount (i.e., 1.7 Gps). Considering that codes in the output stage are once buffered by the external memory, and in view of the overhead for data transfer and LSI costs greatly depending on the number of pins, the above transfer rate and data width are practical at the present stage.
In order to output one kind of coded data from one image input, the conventional image coding apparatus stores plural frame data, such as the prediction image or search image, in one external memory, and carries out the image coding by data transfer with the external memory.
However, according to the conventional image coding apparatus, when the quantity of processing is increased like in a case where two kinds of coded data are outputted from one image input, the bandwidth of the data transfer between the external memory and the coding unit is increased about twice, and thus high-speed transfer or high parallel input is required to construct the image coding apparatus, resulting in an increased system cost. Especially, Formulas (1) and (2) show that the data transfer amount associated with the search range that is employed in the motion vector detection is larger than other data transfer amounts by an order of magnitude.
Further, the motion vector detection circuit that is required for image compressive coding that utilizes the motion compensation inter-frame prediction has a circuit scale that is normally about 10 times greater than those of other circuits that perform processing such as orthogonal transformation (DCT) or variable-length coding, and further the quantity of processing is about 100 times larger. When two of the motion vector detection circuits are provided in the case where two kinds of coded data are to be generated, the circuit scale is increased, and thus the processing time gets longer when this processing is carried out by the same circuit source or program.